# To change this template, choose Tools | Templates
# and open the template in the editor.


module Test
  module Unit
    module Assertions
      class AssertionMessage
        class << self
          def ensure_diffable_string(string)
            string = string.dup.force_encoding("ASCII-8BIT") if string.respond_to?(:encoding) and 
              string.encoding.respond_to?(:ascii_compatible?) and
              !string.encoding.ascii_compatible?
            string
          end
        end
      end
    end
  end  
end

$:.unshift File.join(File.dirname(__FILE__),'..','lib')

require 'test/unit'
require 'clock_v_2_oo_s2'

#der einfachheit halber sei hier der RuntimeError als RT abgekürzt

RT = RuntimeError

class Clock_v_3_test < Test::Unit::TestCase
  
  def test_equal
    assert_equal(true,ClockSec[1].==(ClockSec[1]))
    assert_equal(false,ClockSec[1].==(ClockSec[10]))
    assert_equal(true,Clock24[0, 0, 0].==(Clock24[0, 0, 0]))
    assert_equal(false,Clock24[0, 0, 1].==(Clock24[0, 0, 0]))
    assert_equal(true, Clock12[:AM, 1, 1, 1].==(Clock12[:AM, 1, 1, 1]))
    assert_equal(false, Clock12[:AM, 1, 1, 2].==(Clock12[:AM, 1, 1, 1]))
  end
  
  def test_to_s
    assert_equal("ClockSec[1]", ClockSec[1].to_s)
    assert_equal("Clock24[0,0,0]", Clock24[0,0,0].to_s)
  end
  def test_sec_add
    assert_equal(ClockSec[70], ClockSec[50].clock_sec_add(ClockSec[20])) 
    assert_raise(RT) {ClockSec["40"].clock_sec_add(ClockSec[30])}
    assert_raise(RT) {ClockSec[-10].clock_sec_add()} 
  end

  
   def test_sec_sub 
    assert_equal(ClockSec[70], ClockSec[90].clock_sec_sub(ClockSec[20])) 
    assert_equal(ClockSec[86390], ClockSec[10].clock_sec_sub(ClockSec[20]))
    assert_raise(RT) {ClockSec[30].clock_sec_sub(ClockSec["40"])}
    assert_raise(RT) {ClockSec[-10].clock_sec_sub()} 
  end

  
   def test_sec_succ
    assert_equal(ClockSec[0], ClockSec[86399].clock_sec_succ())
    assert_equal(ClockSec[1], ClockSec[0].clock_sec_succ()) 
    assert_raise(RT) {ClockSec["40"].clock_sec_succ()}
  end
  
  def test_sec_pred
    assert_equal(ClockSec[89], ClockSec[90].clock_sec_pred()) 
    assert_equal(ClockSec[86399], ClockSec[0].clock_sec_pred())
    assert_raise(RT) {ClockSec["40"].clock_sec_pred()}
  end

  
    def test_clock24_to_clocksec
    assert_equal(ClockSec[0], Clock24[0, 0, 0].clock24_to_clocksec())
    assert_equal(ClockSec[36610], Clock24[10, 10, 10].clock24_to_clocksec())
    assert_raise (RT) {Clock24[0, 0, "a"].clock24_to_clocksec()}
    assert_raise (RT) {Clock24[-1, 0, 0].clock24_to_clocksec()}
  end

  
  def test_clock_12_to_clocksec
    assert_equal(ClockSec[0], Clock12[:AM, 12, 0, 0].clock12_to_clocksec())
    assert_equal(ClockSec[43200], Clock12[:PM, 12, 0, 0].clock12_to_clocksec())
    assert_raise (RT) {Clock12[:AM, 0, 0, "a"].clock12_to_clocksec()}
  end


  
 def test_clocksec_to_clock24    
    assert_equal(Clock24[12, 0, 0], ClockSec[43200].clocksec_to_clock24())
    assert_equal(Clock24[13, 13, 13], ClockSec[47593].clocksec_to_clock24())
    assert_raise (RT) {ClockSec["a"].clocksec_to_clock24()} 
  end

  
  def test_clocksec_to_clock12
    assert_equal(Clock12[:AM,12, 0, 0], ClockSec[0].clocksec_to_clock12())
    assert_equal(Clock12[:PM, 1, 13, 13], ClockSec[47593].clocksec_to_clock12())
    assert_raise (RT) {ClockSec["a"].clocksec_to_clock12()}
  end


   def test_clock24_to_clock12
    assert_equal(Clock12[:AM,11,11,11],(Clock24[11,11,11].clock24_to_clock12()))
    assert_equal(Clock12[:PM,1,13,13],(Clock24[13,13,13].clock24_to_clock12()))
    assert_raise (RT) {Clock24[1,1,-1].clock24_to_clock12()}
    end

    


    def test_clock12_to_clock24
    assert_equal(Clock24[11,11,11],Clock12[:AM, 11, 11, 11].clock12_to_clock24())
    assert_equal(Clock24[13,13,13],(Clock12[:PM, 1, 13, 13].clock12_to_clock24()))
    assert_raise (RT) {Clock12[:AM,1,1,-1].clock12_to_clock24()}
    end

    
    
    def test_to_clocksec
      assert_equal(ClockSec[47593], Clock12[:PM, 1, 13, 13].to_clocksec())
       assert_equal(ClockSec[36610], Clock24[10, 10, 10].to_clocksec())
      assert_equal(ClockSec[3000], ClockSec[3000].to_clocksec())
      assert_raise (RT) {ClockSec["a"].to_clocksec()}
    end

    
    
    def test_to_clock12
    assert_equal(Clock12[:AM,12, 0, 0], ClockSec[0].to_clock12())
    assert_equal(Clock12[:PM,1,13,13],(Clock24[13,13,13].to_clock12()))
  assert_equal((Clock12[:PM, 1, 13, 13].to_clock12()),(Clock12[:PM, 1, 13, 13].to_clock12()))  
    assert_raise (RT) {ClockSec["a"].to_clock12()}  
    end


    def test_to_clock24
    assert_equal(Clock24[12, 0, 0], ClockSec[43200].to_clock24())
    assert_equal(Clock24[13, 13, 13], ClockSec[47593].to_clock24())
    assert_equal(Clock24[11,11,11],(Clock12[:AM, 11, 11, 11].to_clock24()))
    assert_equal(Clock24[12, 0, 0],Clock24[12, 0, 0].to_clock24())                    
    assert_raise (RT) {Clock24["a", 0, 0].to_clock24()}
    end

    
    def test_to_clock
      assert_equal(Clock24[12,0,0], Clock24[6,6,6].to_clock(ClockSec[43200]))
      assert_equal(Clock24[12,0,0], Clock24[12,3,1].to_clock(Clock12[:PM,12,0,0]))
      assert_equal(ClockSec[732], ClockSec[10000].to_clock(Clock12[:AM, 12,12,12]))
      assert_equal(ClockSec[43200], ClockSec[10000].to_clock(Clock24[12,0,0]))
      assert_equal(Clock12[:AM, 12,0,0], Clock12[:PM, 1,1,1].to_clock(Clock24[0,0,0]))
      assert_equal(Clock12[:AM, 12,0,0], Clock12[:PM,1,1,1].to_clock(ClockSec[0]))
      assert_raise (RT) {ClockSec["a"].to_clock(Clock12[:AM, 12,0,0])}
    end


    
def test_add_clock
    assert_equal(ClockSec[8600], ClockSec[3000].clock_add(ClockSec[5600]))
    assert_equal(ClockSec[6661], ClockSec[3000].clock_add(Clock24[1,1,1]))
    assert_equal(ClockSec[6661], ClockSec[3000].clock_add(Clock12[:AM,1,1,1]))
    assert_equal(ClockSec[0], ClockSec[86399].clock_add(ClockSec[1]))
    assert_equal(Clock12[:AM,1,17,41], Clock12[:AM,1,1,1].clock_add(ClockSec[1000]))
    assert_equal(Clock12[:AM,2,2,2], Clock12[:AM,1,1,1].clock_add(Clock12[:AM,1,1,1])) 
    assert_equal(Clock12[:AM,2,2,2], Clock12[:AM,1,1,1].clock_add(Clock24[1,1,1]))
    assert_equal(Clock24[1,17,41], Clock24[1,1,1].clock_add(ClockSec[1000]))
    assert_equal(Clock24[2,2,2], Clock24[1,1,1].clock_add(Clock12[:AM,1,1,1])) 
    assert_equal(Clock24[2,2,2], Clock24[1,1,1].clock_add(Clock24[1,1,1]))
    assert_raise (RT) {ClockSec["a"].clock_add(ClockSec[5600])}
    assert_raise (RT) {ClockSec[3000].clock_add(ClockSec["a"])}
   end  
  
def test_clock_succ
    assert_equal(ClockSec[2], ClockSec[1].clock_succ())
    assert_equal(Clock24[1,1,2], Clock24[1,1,1].clock_succ())
    assert_equal(Clock12[:AM,1,1,2], Clock12[:AM,1,1,1].clock_succ())
    assert_raise (RT) {ClockSec["a"].clock_succ()}
  end 

def test_clock_pred
    assert_equal(ClockSec[0], ClockSec[1].clock_pred())
    assert_equal(Clock24[1,1,0], Clock24[1,1,1].clock_pred())
    assert_equal(Clock12[:AM,1,1,0], Clock12[:AM,1,1,1].clock_pred())
    assert_raise (RT) {ClockSec["a"].clock_pred()}
  end    
  
  
def test_clock_day_sec
  assert_equal(3661, Clock12[:AM,1,1,1].clock_day_sec())
  assert_equal(3661, Clock24[1,1,1].clock_day_sec())
  assert_equal(3661, ClockSec[3661].clock_day_sec())
  assert_raise (RT) {ClockSec["3"].clock_day_sec()}
end

def test_clock_sec
  assert_equal(1, Clock12[:AM,1,1,1].clock_sec())
  assert_equal(1, Clock24[1,1,1].clock_sec())
  assert_equal(1, ClockSec[3661].clock_sec())
  assert_raise (RT) {ClockSec["3"].clock_sec()}
end

def test_clock_hour24
  assert_equal(1, Clock12[:AM,1,1,1].clock_hour24())
  assert_equal(1, Clock24[1,1,1].clock_hour24())
  assert_equal(1, ClockSec[3661].clock_hour24())
  assert_raise (RT) {ClockSec["3"].clock_hour24()}
end

def test_clock_hour12
  assert_equal(1, Clock12[:AM,1,1,1].clock_hour12())
  assert_equal(1, Clock24[1,1,1].clock_hour12())
  assert_equal(1, ClockSec[3661].clock_hour12())
  assert_raise (RT) {ClockSec["3"].clock_hour12()}
end

def test_clock_min
  assert_equal(1, Clock12[:AM,1,1,1].clock_min())
  assert_equal(1, Clock24[1,1,1].clock_min())
  assert_equal(1, ClockSec[3661].clock_min())
  assert_raise (RT) {ClockSec["3"].clock_min()}
end

def test_clock_halve
  assert_equal(:AM, Clock12[:AM,1,1,1].clock_halve())
  assert_equal(:AM, Clock24[1,1,1].clock_halve())
  assert_equal(:AM, ClockSec[3661].clock_halve())
  assert_raise (RT) {ClockSec["3"].clock_halve()}
end

end

